Micro/Nano Scale

Latest Innovations

Graphene Classifier

This technology is a classifier based on a ferroelectric graphene transistor. In contrast to traditional current-mode classifiers based on CMOS technologies (which require...

Scalable and Cost-effective Method to Fabricate Quantum Dot Films

Dr. Seok Kim and Dr. Moonsub Shim from the University of Illinois have developed dry means to pattern QD films over large areas with high resolution while maintaining...

Device for the Combination of Semiconductor Processes

Professor Gary Eden from the University of Illinois has developed a device that leverages the recent development of efficient, flat vacuum ultraviolet/ultraviolet lamps to...

High Speed Single-Mode VCSELS

Dr. Milton Feng, from the University of Illinois, has developed single mode Oxide-VCSELs that are able to transmit data signals over longer distances, at higher speeds...

Phase and Intensity Modulator Comprising of a RE-Doped Fiber

Dr. Dragic from the University of IL has developed a phase and intensity modulator using rare earth doped ytterbium fiber. The modulators are unconventional because they...

Carbon Nanotube Portfolio for Manufacturing Applications

This portfolio includes carbon nanotube growth and processing methods relevant to nanotube manufacturing....

Suite of Bioresorbable and Transient Electronics

Optical Inspection of Nanoscale Structures using a Novel Machine Learning Based Synthetic Image Generation Algorithm

Semiconductor defect detection using Machine Learning

Dr. Goddard and Dr. Schwing have developed a machine learning technique which requires only...

Plasma Photonic Crystals Device with Plasmonic Resonances in the Microwave, Millimeter Wave, and Terahertz Spectral Regions

Dr. Eden at the University of Illinois has developed a 3D microplasma photonic crystal which provides the ability to introduce or completely suppress attenuation...

Application Level Hardware Tracing for Scaling Post-Silicon Debug

Dr. Vasudevan from the University of IL has developed an advanced algorithm for optimizing design-for-debug hardware. This algorithm takes advantage of high level...

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