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Home > Hybrid Semiconductor 3D Nanoscale Patterning Metho...(TF09098)

Metal-Assisted Chemical Etching ("MacEtch") of Semiconductors

Hybrid Semiconductor 3D Nanoscale Patterning Metho...(TF09098) [1]

Semiconductor nanostructures have become ubiquitous in consumer electronics, sensing applications, specialized and high-performance materials, and more. These structures are typically produced using slow, expensive, energy-intensive processes such as photolithography and chemical vapor deposition. While some of these processes have become the norm in semiconductor fabrication, the need for increasingly complex devices (and correspondingly longer multistep manufacturing roadmaps drive the need for simpler processes, such as wet chemical etching, to achieve desired semiconductor nanostructures. 

This suite of technologies from the University of Illinois features a scalable, semicon fab-compatible process called "metal-assisted chemical etching (MacEtch) that allows for unprecedented control of semiconductor form factors via a low-cost, energy-efficient technique. MacEtch is performed in a wet etchig environment and uses metal catalysts to selectively remove portions of semiconductor to create nanowires, pores, or a range of other form factors with various aspect ratios and dimensions. MacEtch has been demonstrated for Si, III-V, II-VI and other types of semiconductor materials. Variations of MacEtch approaches in this portfolio include an integrated superionic solid state stamping (S4) approach and a magnetic field-guided etching process that allows for even more unique form factors. MacEtch resolution is on the nanometer scale, with feature sizes often in the tens to hundreds of nanometer range. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects. 

Media

https://compoundsemiconductor.net/article/121079/Revolutionising_semiconductor_etching [2]

Applications

3D nanostructure fabrication will prove useful in the areas of:

  • Batteries, Photovoltaics, Thermoelectrics, Sensors

Benefits

  • Powerful hybrid fabrication technique (top-down approach)
  • Fast (30 sec to a few minutes, depending on depth desired)
  • Performed at room temperature
  • Non-lithographical
  • Low-Cost
  • Scalable
  • Efficient
  • Fabricate both linear and annular patterns (can make circular patterns)
  • High aspect ratios (resolution like no other technique, features down to 15nm range)
Xiuling
Li

Inventors:

US Pat #: 
8980656
Issue Date: 
3/17/2015
US Pat #: 
10134599
Issue Date: 
11/20/2018
US Pat #: 
8810009
Issue Date: 
8/19/2014
US Pat #: 
8486843
Issue Date: 
7/16/2013
US Pat #: 
8951430
Issue Date: 
2/10/2015
US Pat #: 
9704951
Issue Date: 
7/11/2017
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Source URL:https://origin.otm.illinois.edu/technologies/hybrid-semiconductor-3d-nanoscale-patterning-methotf09098

Links
[1] https://origin.otm.illinois.edu/technologies/hybrid-semiconductor-3d-nanoscale-patterning-methotf09098 [2] https://compoundsemiconductor.net/article/121079/Revolutionising_semiconductor_etching