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Gate-All-Around (GAA) Stacked Semiconductor Device

Method of Forming 3D Multi-stack Nanowire and Nanosheet High Electron Mobility Transistors [1]

Since the 1960s, consumers, investors, and businesses have been able to rely on rapid advancement in semiconductor technologies according to Moore's Law, which states that the number of components per semiconductor chip will roughly double every two years with minimal cost increase. For decades, semiconductor manufacturers were able to meet this expectation--and accommodate the huge increase in computing demand--by adopting designs, manufacturing methods, and other technologies that enabled smaller and smaller transistors (the basic building block of semiconductor chips). Continued increases in computing power and performance cannot be achieved in the same way, as today's transistors are so small that downsizing further would compromise the very physics of their operation. The industry has instead pursued increased transistor density by expanding beyond flat, two-dimensional transistor arrays to three-dimensional structures; first via FinFETs in the 2010s and now via even higher-aspect ratio gate-all-around (GAA) technologies. 

Researchers have developed a suite of gate-all-around (GAA) devices to enable high and/or linear performance in a range of electronic applications. One asset encompasses a field effect transistor (FET) featuring between 2 and 20 vertically separated channels with some heterogeneity. The 3D high electron mobility transistor (HEMT) architecture utilizes ultra-wide bandgap (UWBG) materials and can be used for high-power, high-frequency applications. HEMTs can confer an order of magnitude higher performance than wide bandgap (WBG) devices, including simultaneously achieving 10x higher power density while operating at frequencies as high as 120 GHz.

Inventors:

US Pat #: 
9224809
Issue Date: 
12/29/2015
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